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Development of RF-Power Dividers for the Josephson Arbitrary Waveform Synthesizer (JAWS)


To make the existing JAWS set-up more efficient (reducing the number of HF-cables, increasing the number of active Josephson junctions) broadband on-chip power dividers have been developed, which ensure optimal pulse transmission into parallel Josephson circuits.



In JAWS systems, series arrays of SNS Josephson junctions (S: superconductor, N: normal metal) are biased by a high-speed digital sequence of short current pulses, in which the details of the corresponding waveform are encoded by sigma-delta analog-to-digital conversion. These pulse-driven series arrays enable spectrally pure AC voltages to be synthesized in a wide frequency range from a few Hz up to MHz.

Recently two major types of broadband on-chip power dividers were designed at PTB to increase the number of Josephson junctions that are biased by a single channel of the pulse pattern generator. One type of a power divider is a two-stage serial-parallel power divider, which is based on a development at AIST for programmable Josephson voltage standards [1]. We are currently testing its compatibility in the JAWS circuits. The second type is a one-stage Wilkinson power divider, which has been implemented in a different version into the NIST JAWS circuits [2]. Each output of the power divider is equipped with an extra on-chip DC-block capacitor. Different designs were numerically simulated in CST Microwave Studio. The most promising configurations were selected, integrated to the JAWS circuit layouts and fabricated in the PTB clean room center.

The on-chip power dividers were investigated in first measurements at a low temperature of 4.2 K using the PTB’s 8-channel JAWS setup. Our measurement results showed that all Josephson junctions were properly biased using RTZ-pulses (≤ 15 GHz), and the first order Shapiro steps were clearly formed for both types of splitter. Figure a) illustrates that the test chips containing a two-stage serial-parallel power divider and 2000 Josephson junctions are operational, however, up to a maximal clock frequency of 8 GHz only as further measurements have shown. Additionally, a spectrally pure synthesized sinusoidal waveform could be achieved with sigma-delta code amplitudes up to 30 % only. Based on these results, the circuit layout should be altered and optimized in the next iteration step. Figure b) demonstrates that the on-chip one-stage Wilkinson power divider is operating up to a clock frequency of 15 GHz. With a total number of 1000 Josephson junctions, we successfully synthesized spectrally pure sinusoidal waveforms with output voltages of 11.7 mV (RMS), and stable operation margins of 740 µA were achieved. Thus, we plan to integrate multi-stacked Josephson junctions with Wilkinson power divider soon.

The power dividers will be used for operation of a larger number of Josephson junctions in future to increase the output voltage that is generated by a single chip.

Frequency spectrum of a test chip


Frequency spectrum of a test chip

Figure: Frequency spectrum of a test chip with a 2-stage serial-parallel power divider and 2000 Josephson junctions (a) with a 1-stage Wilkinson power divider and 1000 Josephson junctions (b)