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Multilayer sandwich

Stacked Josephson junctions for the pulse-driven quantum voltage standard

PTB News 2.2021
26.03.2021
Especially interesting for

metrology institutes

calibration laboratories

manufacturers of precision electrical measuring instruments

Josephson arbitrary waveform synthesizers (JAWS) allow quantized AC voltages to be synthesized with arbitrary and spectrally pure waveforms. At PTB, a pulse-driven Josephson standard for the generation of AC voltages with series arrays has been realized. These arrays are based on stacks of up to five Josephson junctions. This new technology has allowed the integration density of the circuits – and thus their output voltage – to be considerably increased: With up to 30 000 junctions per chip, it is now possible to generate an effective voltage of 0.5 V RMS (0.7 V peak). The yield of the fabrication process has been clearly increased by adapting various parameters.

SEM image of a series array with 5 stacked Josephson junctions (cross section view). The height of the junction stacks amounts to approx. 800 nm; all layers taken together are roughly 3 μm in height.

Pulse-driven Josephson AC voltage standards enable a large number of metrological applications and are based on series arrays of superconducting Josephson junctions of the kind manufactured in the Clean Room Center of PTB. In the long run, it is planned that the output voltage will be further increased to reach values between 7 V and 10 V to extend the range of possible applications.

One of the measures envisaged in order to achieve such an increase consists in raising the integration density of Josephson junctions on the chips. Since the junctions are integrated into a high-frequency structure (a coplanar waveguide), the possibility to increase the length of the series array is limited. To increase the number of junctions on each chip, the junctions were stacked vertically. This was made technologically possible by the material layer combination of the Josephson junctions, which consist of Nb and Si.

After several modifications and enhancements of the standard process used at PTB, which is based on electron beam lithography, stacks of up to 5 Josephson junctions have now been successfully implemented with a high process yield. Two important process enhancements are worth mentioning in this context: For one thing, a chemical-mechanical polishing procedure was introduced for the planarization of the array surfaces. Thanks to this procedure, the successive superconducting layers can be deposited and then structured in compliance with high quality requirements (high superconducting current carrying capacity). For another, a non-conducting silicon oxide layer was deposited between the electrically conducting structures by means of atomic layer deposition (ALD) in collaboration with the Leibniz Institute of Photonic Technology (IPHT) in Jena. Contrary to the silicon oxide non-conducting layers that had previously been manufactured at PTB by means of plasma-enhanced chemical vapor deposition, ALD layers have the advantage of covering edges perfectly. They thus provide good edge isolation even at extreme aspect ratios such as those prevailing in 5-fold stacks of junction arrays.

PTB is planning to make the ALD technology available in its own Clean Room Center in the future. All in all, the complex fabrication process in which 30 000 Josephson junctions are integrated onto a chip with a surface of (10 × 10) mm2 consists in depositing 16 layers in approx. 40 individual process steps.

Contact

Oliver Kieler
Department 2.4
Quantum Electronics
Phone: +49 531 592-2410
Opens local program for sending emailoliver.kieler(at)ptb.de

Scientific publication

O. Kieler, R. Wendisch, R. Gerdau, T. Weimann, J. Kohlmann, R. Behr: Stacked Josephson junction arrays for the pulse-driven AC Josephson voltage standard. IEEE Trans. Appl. Supercond. 31 (2021)