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Ultra-fast magnetic memories

In the future, a new bit-triggering procedure developed at PTB will enable non-volatile magnetic memory components (i.e.: magnetic random access memory: MRAM) access times below 500 ps. This means that, for the first time, a non-volatile memory chip would be as fast as the fastest volatile memory components.

4MBit MRAM Chip of the firm of freescale (formerly Motorola)

Fast memory chips commonly used today such as DRAMs and SRAMs have one decisive disadvantage: in case of power supply interruption, they lose their stored information. MRAMs promise to solve this problem. The digital information in a MRAM is stored as a magnetization direction in magnetic cells and not an electrical charge status. All large chip producers are participating in the development of this novel memory chip. Launching of the chip is imminent.

At present, MRAM programming of a magnetic bit takes, however, about 10 ns. Faster operation has hitherto been impeded by a physical property of the magnetic memory cells: when writing a specific cell in the MRAM chip, magnetic excitations also occur in a great number of other cells. These excitations are only weakly damped and need up to 10 ns to die out. During this time, no other cell can be programmed so that the maximum clock rate of the MRAM is limited to approx. 100 MHz.

With the aid of a bit-triggering procedure developed at PTB and for which a patent has been applied, this limitation of the MRAM clock rate can now be avoided. In the case of the so-called “ballistic bit triggering”, magnetic excitations in all cells of the MRAM are avoided almost completely by skilful selection of the magnetic pulses used for programming.

The pulses are selected in such a way that magnetization of the cell to be switched performs half (180°) a precession rotation, while a full (360°) precession rotation occurs in the cell, whose memory state is to remain unchanged. In both cases, magnetization is in equilibrium after switch-off of the pulses and additional magnetic excitations no longer occur.

This optimal bit triggering can be performed with very short switching pulses (duration below than 500 ps), which leads to maximum MRAM clock rates of more than 2 GHz. Construction of a non-volatile memory component, the clock rate of which can compete with the fastest volatile memory components – the SRAM – is possible for the first time. Parallel programming of several bits at the same time could increase the effective MRAM write rate per bit even by another order of magnitude.